Although applicable to arbitrary semiconductor structures, the present invention and also the problem area on which it is based are explained on the basis of trenches for storage capacitors in semiconductor memory devices.
Modern semiconductor memory devices have trench capacitors in order that the individual memory cells comprising the trench capacitor and an associated selection transistor have a least possible space requirement.
Since the capacitance of a trench capacitor is directly proportional to its surface area, the trenches of the trench capacitors are usually expanded by an etching process in the lower region, which results in a desired enlargement of the surface area.
FIGS. 2–4 show process steps of a method for expanding a trench in a semiconductor structure which is disclosed in US 2001/0016398 A1.
In FIG. 2, reference symbol 100 designates a silicon semiconductor substrate with a trench 50 provided therein. Situated on the surface of the silicon semiconductor substrate 100 is a pad stack 110, comprising a lower pad oxide layer 111 and an upper pad nitride layer 112, which have been used as a mask for forming the trench 50. An insulation collar 120 made of silicon, e.g. TEOS oxide, is provided in the upper trench region 154.
The semiconductor structure with the trench 50 shown in FIG. 2 is firstly treated with HF in order to remove natural oxide from the silicon surfaces 150 that are uncovered in the trench 50 and to terminate these silicon surfaces 150 with hydrogen, which remains on the silicon surfaces 150.
The HF treatment is preferably carried out for 60 to 180 seconds in a water/HF solution having a volume ratio of 200:1.
In a subsequent process step, illustrated in FIG. 3, firstly a rinsing with H2O is effected and then an anisotropic wet etching with alkaline NH4OH solution is effected, for example in an aqueous solution with a dilution of 100:1.
In this case, the trench 50 is expanded in the lower region 155 lying below the insulation collar 120. The diagrammatic drawing of FIG. 3 does not illustrate the fact that the expansion is effected anisotropically with regard to specific crystal planes in a manner dependent on the crystal orientation of the silicon semiconductor substrate 100.
Furthermore referring to FIG. 4, after a desired expansion has been obtained, the NH4OH is removed from the trench 50 by rinsing with H2O.
The H2O rinsing gives rise to problems, however, in so far as dissolved SiO2 precipitates as silica gel as a result of the negative pH shift of the water rinsing and forms complexes which can outdiffuse significantly more slowly than protons of the water rinsing can indiffuse. In other words, these precipitated complexes impede rapid rinsing of the trench 50, which has the effect that the etching in the lower trench region, where new protons can be supplied only slowly, advances in an uncontrolled manner until the complexes have outdiffused.
The mechanisms of the NH4OH etching and of the subsequent water rinsing are reproduced by the corresponding chemical formulae below.    a) NH4OH etching of silicon4OH−+Si→SiO2(OH)2−2aq.+2H++4e−(alkaline stablized SiO2)4e−+4H2O→4OH−+2H2    b) Water rinsing: negative pH shift→protonation of silica gel→destabilizationSiO2(OH)22−+2H+→Si(OH)4→Si(OH)3−O−Si(OH)3+H2O(condensation)
A typical value of the diffusion coefficient for the protons is 12×10−9 m2s−1 and a typical value of the diffusion coefficient for SiOX is 0.5×10−9 m2s−1.
Possible approaches for solving this problem might provide downstream HF etches that bring dissolved SiO2 into solution again. The disadvantage consists in the consumption of SiO2, that is to say also in an attack on the insulation collar 120. The etching rate is not significantly lowered by a dilution of the etching solution, for example 400:1 instead of 100:1. At lower temperatures, although the etching rate decreases, the solubility of SiO2 likewise decreases.